This file documents the function of various jumpers that were added to the boards when applying the patches.

Card_A

 Patch 5: COMPATIBILITY WITH BUS SHARING SCHEMES
 SJ8 open(default) = drive bus during Phase 1 and Phase 2
 SJ8 closed        = drive bus during Phase 2 only.

 Category: Recommended

 Rationale: Required for operation in machines that implement bus sharing schemes (e.g. Commodore 64)

 Description: The C74-6502 was designed to drive the bus during Phase 1 only. This is in order to avoid
 transient bus collisions at high speeds. Unfortunately, this bus scheme is not compatible with systems
 where the CPU shares control of the bus with other peripherals (such as on the Commodore 64 and
 others). This patch will cause the CPU to drive the bus during Phase 2 as well as Phase 1. This will lead
 to short transient collisions one the bus during state transitions, but these are benign and can be safely
 ignored.

 Note: Need to test whether applying this patch inhibits operation at the highest clock-rates. If so, consider replacing
 ADL.A and ADH.A 74CBT3245s with 74AC541s.


 Patch 7: NMOS 6502 MODIFY CYCLE WRITE
 SJ5 open(default) = H+1 instable NMOS6502 opcodes disabled
 SJ5 closed        = H+1 instable NMOS6502 opcodes enabled, DPH+1 fed from WR.MX1.DPH+

 Category: Recommended

 Rationale: Several Commodore 64 games were found to rely on a Modify-Cycle-Write to clear the raster
 interrupt on the VICII chip. This is fairly common practise on more advanced games. Most 65C02 systems
 will work when the NMOS Modify-Cycle-Write behaviour is in effect. However, the reverse is not true. It is
 therefore recommended that the patch be made unless operation on NMOS 6502 systems is not planned.

 Description: The NMOS 6502 performs a Read-Write-Write sequence for RMW instructions (INC, DEC,
 ASL, etc.). The C74-6502 was designed to duplicate the 65C02 behaviour, which is Read-Read-Write.
 This patch will cause a Write to be performed during the Modify (middle) cycle when the NMOS 6502
 instruction-set is selected.

 WARNING: This patch disables H+1 undocumented opcodes (see C74-6502 datasheet p. 21). These opcodes are classified as
 unstable, meaning that they produce different results on different 6502 systems. Their use is extremely rare. The C74-6502
 implementation is detailed in the datasheet (Appendix F). They are not supported at clock-rates above 14MHz.


 Patch 8: DEAD-CYCLE  NMOS VS. CMOS COMPATIBLE BEHAVIOUR
 SJ7 open(default) = SJ6 closed is pre-load AD.MX for DPH.=DPH+1 (avoids collisions when switching back)
 SJ7 closed        = SJ6 open is NMOS compatibility, SJ6 closed = CMOS compatibility

 Category: Optional

 Rationale: Although this is rare, some software on NMOS 6502 systems relies on partial addresses reads
 during the dead-cycle. This patch is optional. It should be made if strict compatibility with NMOS 6502 is
 desired. Once applied, close SJ6 for CMOS compatibility, and leave it open for NMOS
 compatibility.

 Description: The NMOS 6502 produces partial addresses on the bus during address calculation. This
 was changed on the 65C02, which leaves in place the Previous Bus Address in those situations. This
 patch enables the *DP jumper to select between these two behaviours, leaving the jumper open for
 NMOS compatible operation, and closing it for CMOS operation.

 WARNING: This patch requires that ADL.A and ADL.H be replaced with 74AC245s (rather than 74CBT3245s) when operating as a
 65C02 in systems which implement a bus sharing scheme (i.e., where the CPU does not have complete control of the address bus).

Card_B

 Patch 7: NMOS 6502 MODIFY CYCLE WRITE
 SJ10 open(default) = H+1 instable NMOS6502 opcodes disabled
 SJ10 closed        = H+1 instable NMOS6502 opcodes enabled, DPH+1 fed from (ML.LATCHA & NMOS)
 //Don't close Card_A SJ5 and Card_B SJ10 at the same time.

 Category: Recommended

 Rationale: Several Commodore 64 games were found to rely on a Modify-Cycle-Write to clear the raster
 interrupt on the VICII chip. This is fairly common practise on more advanced games. Most 65C02 systems
 will work when the NMOS Modify-Cycle-Write behaviour is in effect. However, the reverse is not true. It is
 therefore recommended that the patch be made unless operation on NMOS 6502 systems is not planned.

 Description: The NMOS 6502 performs a Read-Write-Write sequence for RMW instructions (INC, DEC,
 ASL, etc.). The C74-6502 was designed to duplicate the 65C02 behaviour, which is Read-Read-Write.
 This patch will cause a Write to be performed during the Modify (middle) cycle when the NMOS 6502
 instruction-set is selected.

 WARNING: This patch disables H+1 undocumented opcodes (see C74-6502 datasheet p. 21). These opcodes are classified as
 unstable, meaning that they produce different results on different 6502 systems. Their use is extremely rare. The C74-6502
 implementation is detailed in the datasheet (Appendix F). They are not supported at clock-rates above 14MHz.
